Photoresist is a light-sensitive material used in photolithography to form a patterned layer on a surface. In a positive resist, the portion of the photoresist that is exposed to light becomes soluble to a photoresist developer. The portion of the photoresist that is unexposed remains insoluble to the photoresist developer. In a negative resist, the portion of the photoresist that is exposed to light becomes insoluble to the photoresist developer. The portion of the photoresist that is unexposed is dissolved by the photoresist developer. The light used for developing photoresist includes ultraviolet (UV) or deep UV (DUV) light, wherein shorter wavelengths allow a reduced aspect ratio and hence a smaller minimum feature size to be achieved. The patterned photoresist is used to perform one or more subsequent processes on or in the underlying semiconductor layer. Thus, the fidelity of the patterned resist directly affects the resulting geometry of the underlying layer.
Light scattering from non-planar wafer topography substrates can cause light exposure in photoresist areas normally unexposed. FIG. 1 illustrates an exemplary substrate 101 including a plurality of non-planar topology features. These features include a shallow trench isolation (STI) area 102A and a polysilicon feature 104A, each of which can reflect light at different angles and affect the exposure of a desired patterned resist feature 103A. This scattered light tends to cause disruptions in pattern fidelity of the photoresist. These disruptions are called wafer substrate topography proximity effects (TPE) in the industry. For example, in the case of patterned resist 103A, the scattered light from STI 102A and polysilicon features 104A may result in a different critical dimension (CD) at the bottom than at the top. This CD variation may undesirably affect the CD transferred to the underlying area during a subsequent process.
Note that state-of-the-art integrated circuit (IC) designs are increasingly complex. Therefore, dense patterns rather than sparse patterns are increasingly prevalent in IC designs. For dense patterns, the wafer topography sensitivity of the photoresist CD appears to be more pronounced compared to sparse patterns due to the scattering of light described above. Therefore, the TPE problem is expected to worsen as IC designs continue to evolve in complexity.
TPE has been ignored for 45 nm and larger node technologies due to its relatively small impact to pattern CDs. For smaller node technologies, bottom anti-reflective coatings (BARCs) have been used in conjunction with photoresists to mitigate TPE. However, for an implant layer patterning step, BARC is not a preferred solution due to increased implant process complexity. Therefore, for 32 nm and 28 nm node technologies, rule-based correction or mask-based correction of TPE-induced CD variations can be used for the implant layer. However, for 20 nm node and below technologies, even more accurate TPE modeling becomes both desirable and necessary.
Tools to simulate photolithography effects are currently available. For example, the Sentaurus™ lithography (S-Litho™) tool provided by Synopsys, Inc. can accurately simulate wafer substrate topography proximity effects by solving Maxwell's equations. As known by those skilled in the art, Maxwell's equations are a set of partial differential equations that, together with the Lorentz force law, provide the rudiments of accurately estimating optical effects, including photolithography. Unfortunately, this approach is computationally intensive, and therefore has long runtimes. As a result, this approach is unsuitable for full-chip applications.
Therefore, a fast method for TPE modeling is needed to make full-chip TPE correction feasible.